[libre-riscv-dev] daily kan-ban update 13may2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed May 13 16:03:21 BST 2020

On Wed, May 13, 2020 at 3:43 PM Tobias Platen
<libre-soc at platen-software.de> wrote:
> On Wed, 13 May 2020 15:33:53 +0100
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> > a really useful self-contained sub-task would be to convert this to nmigen:
> > https://github.com/antonblanchard/microwatt/blob/master/countzero.vhdl
> I think I could do this in an hour or less.

ok great.  create a directory in soc.git, src/soc/countzero to work in.
don't commit the VHDL to the repo, reference it in a comment at the top
of countzero.py

also useful as a "very basic" simulation and confirmation of functionality
i'd recommend doing a unit test similar to countzero_tb.vhdl


More information about the libre-riscv-dev mailing list