[libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance

[Hugh Blemings]

Hi All,

I'm barely qualified to add much more than $0.20 to this thread, but 
will give it a whirl...

I've not had a chance to dig into the v3.1 spec as yet but can offer the 
observation that the intent (as demonstrated in the Microwatt 
implementation for example) was that the simpler/simplest 
implementations would be LE with BE optional. SIMD also optional in 
these as well.

So if the docs don't represent this we'll need to take a closer look :)

We're getting more of the key folk from our member companies (mostly 
IBM) into the loop through this list but as Luke rightly pointed out 
over on libre-riscv-dev they're a busy crew at the moment with a new 
chip due out soon :)

That said I imagine someone will chime in soon who -actually- knows this 
stuff!

Cheers,
Hugh

(Speaking for myself only in this case, though I believe wearing my ED 
hat I'd be saying much the same :)


On 12/5/20 5:24 pm, Jacob Lifshay wrote:
> Over on Libre-SOC's mailing list (CCed), we've been having a 
> conversation about the newly-released spec v3.1 and the compliance 
> levels:
> http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006502.html
>
> we are building a cpu that is intended to be Linux capable, however 
> doesn't support Power's SIMD instructions and is LE only. We've been 
> running into an issue with the spec's compliance levels:
> the linux compliance level requires SIMD and BE is optional but the 
> lower compliance levels require BE but SIMD is optional.
>
> Would it be possible to get a LE version of the int and int+float 
> compliance levels added to the spec?
>
> Other ideas also welcome
>
> Jacob Lifshay
>
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