[libre-riscv-dev] Introduction and Questions

Yehowshua yimmanuel3 at gatech.edu
Fri May 15 20:33:51 BST 2020

> On May 15, 2020, at 3:15 PM, Jeremy Singher <thejsingher at gmail.com> wrote:
> Are you targeting IPC as the performance metric? Or IPC x Freq?
> The Pi 1 Rev B seems to be a 1-wide in-order design, so it should be a
> pretty conservative target to hit.
> Any basic OOO core should beat the PI B in IPC, it only needs to run
> at an equivalent frequency.
> Do you know what the final performance target is? (Or minimal target
> for a commercially viable product?)
> The Cortex A72 is a 3-w OOO that might be a good point to target (it's
> also used the latest Pi 4s).
> From running a couple experiments on other open-OOO cores, it seems
> like 3-ish DMIPs/MHz is a good
> target for a OOO core.

I know we initially were targeting 5GFLOPS for the GPU on the first tapeout.

Basically, the way we’re doing the GPU is the add a vector FPU along with
accompanying instructions into the actual CPU.

We would then just write the drivers that translate various shaders and drawing
commands into vector instructions which can be scheduled on the scoreboard.

Realistically, for our first tapeout(we’re using Google’s shuttle service on 1800nm TSMC),
we’d do a CPU with no vector instructions(effectively no GPU) for October.

Since we’re doing FOSS down to the VLSI design cells(we’re using Time Ansell’s OpenPDK as an intermediate), we need somebody to do a PLL.

With a FOSS PLL in place, we can get 300MHZ on the first tapeout. We’re doing a single core for the 
first tape out, with 6 stages I think…

With no PLL, I think we’re limited to 25-50MHz.

Some simple math could give a DMIPS estimate.


More information about the libre-riscv-dev mailing list