[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
register allocations, for fu.div.pipe_data.py

looks to be identical to ALUInputData and ALUOutputData.

https://libre-soc.org/openpower/isa/fixedarith/

# Divide

XO-Form   divw* RT,RA,RB

Special Registers Altered:

* CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
* SO OV OV32  (if OE=1)

# Modulo

X-Form  mod* RT,RA,RB

no special regs altered

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