[libre-riscv-dev] daily status update 05may2020

Yehowshua yimmanuel3 at gatech.edu
Tue May 5 14:02:45 BST 2020

> On May 5, 2020, at 6:47 AM, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> yesterday i got the preliminary / testing L0CacheBuffer up and
> running:


> the important bit being the PortInterface class which
> connects to the LD/ST Computational Units.

What exactly is a LDSTCompUnit? A cursory Google search just brings up Libre-SOC.
Does it take a LD/ST instruction and compute the offset before access?

Why do you call it cache buffer - I’ve only heard the term cache.

Also, how many ways is the cache? Is it configureable - are you pulling in the source from minerva?

> today i'll be working on the redesigned LD/ST Computational Unit which
> has 3R-2W (indexed and update) capability.
> https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg <https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg>
Can we have a link to the gittree for this code.

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