June 2020 Archives by author

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Starting: Mon Jun 1 03:03:52 BST 2020
Ending: Tue Jun 30 19:43:49 BST 2020
Messages: 889

• [libre-riscv-dev] Fwd: programmerjake mentioned you in Intel Details Lakefield With Hybrid Technology   lkcl .
• [libre-riscv-dev] libre-soc exim4 wouldn't talk to gmail for 2-3 days   lkcl .
• [libre-riscv-dev] libre-soc exim4 wouldn't talk to gmail for 2-3 days   lkcl .
• [libre-riscv-dev] Kazan status   Anton Bondarev
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Hendrik Boom
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Hendrik Boom
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Hendrik Boom
• [libre-riscv-dev] why developers love rust on stackoverflow blog   Hendrik Boom
• [libre-riscv-dev] why developers love rust on stackoverflow blog   Hendrik Boom
• [libre-riscv-dev] Fall 2022 Interfaces   Hendrik Boom
• [libre-riscv-dev] 2pm UK time, 17 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Hendrik Boom
• [libre-riscv-dev] Introduction   Hendrik Boom
• [libre-riscv-dev] *DAY MOVED* 2pm UK time, 18 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Hendrik Boom
• [libre-riscv-dev] renaming master branch   Hendrik Boom
• [libre-riscv-dev] bountysource and problems with new terms of service   Bountysource
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Lauri Kasanen
• [libre-riscv-dev] Kazan status   Lauri Kasanen
• [libre-riscv-dev] Introduction   Lauri Kasanen
• [libre-riscv-dev] IBM releases A2I core VHDL   Lauri Kasanen
• [libre-riscv-dev] https://europeanstartups.co/about   Dan Leighton
• [libre-riscv-dev] more pipeline instructions needed   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Named Records in nMigen   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 01jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] microwatt decoder tables: M-Form and X-Form switched RS and RB   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 01jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 01jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 01jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] microwatt decoder tables: M-Form and X-Form switched RS and RB   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 01jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 01jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 02jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] microwatt decoder tables: M-Form and X-Form switched RS and RB   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 02jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 02jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 02jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 01jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 02jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 02jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder tables: M-Form and X-Form switched RS and RB   Luke Kenneth Casson Leighton
• [libre-riscv-dev] googleusercontent looks like it got hacked yesterday   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 03jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] regfile-to-function-unit connection taking shape   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Move FHDLTestCase to our utils folder   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 03jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 03jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] using a stage chain in a stage   Luke Kenneth Casson Leighton
• [libre-riscv-dev] using a stage chain in a stage   Luke Kenneth Casson Leighton
• [libre-riscv-dev] using a stage chain in a stage   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 03jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 04jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 04jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 04jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 04jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 04jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] publish crowdsupply update ourselves   Luke Kenneth Casson Leighton
• [libre-riscv-dev] tobias: note the comment here in bug #216   Luke Kenneth Casson Leighton
• [libre-riscv-dev] NLNet018TV documentation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 05jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 05jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] GPU Drivers ROCM   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 05jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 06jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction and Questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Contributing to the Libre-Soc Project   Luke Kenneth Casson Leighton
• [libre-riscv-dev] FHDLTestCase   Luke Kenneth Casson Leighton
• [libre-riscv-dev] FHDLTestCase   Luke Kenneth Casson Leighton
• [libre-riscv-dev] FHDLTestCase   Luke Kenneth Casson Leighton
• [libre-riscv-dev] FHDLTestCase   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Successful subscription   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard Tests   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 07jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] "simple" core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] "simple" core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] "simple" core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] "simple" core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Using formal to expose bugs in scoreboard   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Understanding the LibreSOC core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Understanding the LibreSOC core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Understanding the LibreSOC core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Understanding the LibreSOC core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Understanding the LibreSOC core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Understanding the LibreSOC core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Understanding the LibreSOC core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Understanding the LibreSOC core   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 09jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 09jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 09jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] mortbopet/Ripes: A graphical processor simulator and assembly editor for the RISC-V ISA   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 09jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 09jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 09jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 09jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] AMD ISAs   Luke Kenneth Casson Leighton
• [libre-riscv-dev] AMD ISAs   Luke Kenneth Casson Leighton
• [libre-riscv-dev] why developers love rust on stackoverflow blog   Luke Kenneth Casson Leighton
• [libre-riscv-dev] why developers love rust on stackoverflow blog   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 09jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 10jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LDST compunit semi operational   Luke Kenneth Casson Leighton
• [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 10jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 11jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 11jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST now a bit better. extra NLNet budgets   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST now a bit better. extra NLNet budgets   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Handling POWERVec Instructions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] openpower virtual coffee now   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Fall 2022 Interfaces   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Fall 2022 Interfaces   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Kazan status   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 11jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Fall 2022 Interfaces   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 12jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 12jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Fall 2022 Interfaces   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Fall 2022 Interfaces   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 13jul2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] effects of powered-off chip sections on current leakage   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] bugzilla tracking messages now moved to libre-soc-bugs at libre-soc.org   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Minerva L1 Cache   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Minerva L1 Cache   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Minerva L1 Cache   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 15jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] 2pm UK time, 17 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Luke Kenneth Casson Leighton
• [libre-riscv-dev] 2pm UK time, 17 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Minerva L1 Cache   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 15jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Minerva L1 Cache   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Minerva L1 Cache   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction   Luke Kenneth Casson Leighton
• [libre-riscv-dev] 2pm UK time, 17 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 15jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 15jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Minerva L1 Cache   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Yehowshua Tasks   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction   Luke Kenneth Casson Leighton
• [libre-riscv-dev] using debian on a mac   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Minerva L1 Cache   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Minerva L1 Cache   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 15jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Yehowshua Tasks   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Yehowshua Tasks   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 16jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] *DAY MOVED* 2pm UK time, 18 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Luke Kenneth Casson Leighton
• [libre-riscv-dev] *DAY MOVED* 2pm UK time, 18 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Luke Kenneth Casson Leighton
• [libre-riscv-dev] first version of test issuer is functional   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 16jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 17jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] first version of test issuer is functional   Luke Kenneth Casson Leighton
• [libre-riscv-dev] *DAY MOVED* 2pm UK time, 18 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Luke Kenneth Casson Leighton
• [libre-riscv-dev] test issuer core now functional, running loops   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 17jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 17jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 18jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Very Subtle Synchronous nMigen Behavior   Luke Kenneth Casson Leighton
• [libre-riscv-dev] *DAY MOVED* 2pm UK time, 18 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Very Subtle Synchronous nMigen Behavior   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Enabling Small images on the mailing list   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Very Subtle Synchronous nMigen Behavior   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Yehowshua Tasks   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Yehowshua Tasks   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Yehowshua Tasks   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libre-soc exim4 wouldn't talk to gmail for 2-3 days   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Yehowshua Tasks   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 18jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 19jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 17jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Yehowshua Tasks   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Yehowshua Tasks   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Yehowshua Tasks   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Yehowshua Tasks   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 20jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Tests in soc/fu   Luke Kenneth Casson Leighton
• [libre-riscv-dev] nMIgen now generates C++ models through yosysCXX!!!   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Fwd: nMigen meetings   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard and LDST questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Fwd: [Libre-silicon-devel] Competition to LS: Skywater 130nm production-ready PDK gets opensourced   Luke Kenneth Casson Leighton
• [libre-riscv-dev] renaming master branch   Luke Kenneth Casson Leighton
• [libre-riscv-dev] renaming master branch   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 19jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] nMIgen now generates C++ models through yosysCXX!!!   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Very Subtle Synchronous nMigen Behavior   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Tests in soc/fu   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Tests in soc/fu   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Tests in soc/fu   Luke Kenneth Casson Leighton
• [libre-riscv-dev] vulkan driver for broadcom videocore iv   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Tests in soc/fu   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 21jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Tests in soc/fu   Luke Kenneth Casson Leighton
• [libre-riscv-dev] types of contract and their application in out-of-order processors   Luke Kenneth Casson Leighton
• [libre-riscv-dev] types of contract and their application in out-of-order processors   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard and LDST questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libre-soc exim4 wouldn't talk to gmail for 2-3 days   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard and LDST questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard and LDST questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard and LDST questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard and LDST questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] vulkan driver for broadcom videocore iv   Luke Kenneth Casson Leighton
• [libre-riscv-dev] mythic-beasts offered an upgrade for the virtual server behind libre-soc.org   Luke Kenneth Casson Leighton
• [libre-riscv-dev] vulkan driver for broadcom videocore iv   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Tests in soc/fu   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Tests in soc/fu   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 22jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 22jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] distributed bugtrackers   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] https://slashdot.org/story/20/06/23/1548205/amazon-unveils-2-billion-fund-to-invest-in-startups-building-sustainable-technology   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] https://slashdot.org/story/20/06/23/1548205/amazon-unveils-2-billion-fund-to-invest-in-startups-building-sustainable-technology   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] https://europeanstartups.co/about   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Enabling Small images on the mailing list   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libresoc memory architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] openpower summit update, jun 30   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Fwd: [Git][vlsi-eda/coriolis][devel] The VST driver may suppress linkage type.   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Git][vlsi-eda/coriolis][devel] The VST driver may suppress linkage type.   Luke Kenneth Casson Leighton
• [libre-riscv-dev] ASIC layout questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] ASIC layout questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Intel Skylake QA "abnormally bad"   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Intel Skylake QA "abnormally bad"   Luke Kenneth Casson Leighton
• [libre-riscv-dev] ASIC layout questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] clash, haskell, and a 6502 processor   Luke Kenneth Casson Leighton
• [libre-riscv-dev] openpower virtual coffee 3 mins   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 25jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 25jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 25jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] nmigen docs pushed online   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 27jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 27jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 28jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 28jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 28jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 28jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 29jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 29jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 29jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] IBM releases A2I core VHDL   Luke Kenneth Casson Leighton
• [libre-riscv-dev] IBM releases A2I core VHDL   Luke Kenneth Casson Leighton
• [libre-riscv-dev] IBM releases A2I core VHDL   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 30jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 30jun2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 01jun2020   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 02jun2020   Jacob Lifshay
• [libre-riscv-dev] using a stage chain in a stage   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 03jun2020   Jacob Lifshay
• [libre-riscv-dev] using a stage chain in a stage   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 04jun2020   Jacob Lifshay
• [libre-riscv-dev] publish crowdsupply update ourselves   Jacob Lifshay
• [libre-riscv-dev] publish crowdsupply update ourselves   Jacob Lifshay
• [libre-riscv-dev] NLNet018TV documentation   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 05jun2020   Jacob Lifshay
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 09jun2020   Jacob Lifshay
• [libre-riscv-dev] AMD ISAs   Jacob Lifshay
• [libre-riscv-dev] why developers love rust on stackoverflow blog   Jacob Lifshay
• [libre-riscv-dev] why developers love rust on stackoverflow blog   Jacob Lifshay
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 10jun2020   Jacob Lifshay
• [libre-riscv-dev] Kazan status   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 11jun2020   Jacob Lifshay
• [libre-riscv-dev] Fall 2022 Interfaces   Jacob Lifshay
• [libre-riscv-dev] Fall 2022 Interfaces   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 12jun2020   Jacob Lifshay
• [libre-riscv-dev] effects of powered-off chip sections on current leakage   Jacob Lifshay
• [libre-riscv-dev] effects of powered-off chip sections on current leakage   Jacob Lifshay
• [libre-riscv-dev] using debian on a mac   Jacob Lifshay
• [libre-riscv-dev] Introduction   Jacob Lifshay
• [libre-riscv-dev] L1 cache and GPU workloads   Jacob Lifshay
• [libre-riscv-dev] Introduction   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 15jun2020   Jacob Lifshay
• [libre-riscv-dev] Abuse on salsa.debian.org from user programmerjake-guest   Jacob Lifshay
• [libre-riscv-dev] Abuse on salsa.debian.org from user programmerjake-guest   Jacob Lifshay
• [libre-riscv-dev] bountysource and problems with new terms of service   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 17jun2020   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 18jun2020   Jacob Lifshay
• [libre-riscv-dev] Very Subtle Synchronous nMigen Behavior   Jacob Lifshay
• [libre-riscv-dev] libre-soc exim4 wouldn't talk to gmail for 2-3 days   Jacob Lifshay
• [libre-riscv-dev] renaming master branch   Jacob Lifshay
• [libre-riscv-dev] libre-soc exim4 wouldn't talk to gmail for 2-3 days   Jacob Lifshay
• [libre-riscv-dev] renaming master branch   Jacob Lifshay
• [libre-riscv-dev] Tests in soc/fu   Jacob Lifshay
• [libre-riscv-dev] libresoc memory architecture   Jacob Lifshay
• [libre-riscv-dev] libresoc memory architecture   Jacob Lifshay
• [libre-riscv-dev] libresoc memory architecture   Jacob Lifshay
• [libre-riscv-dev] libresoc memory architecture   Jacob Lifshay
• [libre-riscv-dev] libresoc memory architecture   Jacob Lifshay
• [libre-riscv-dev] openpower virtual coffee 3 mins   Jacob Lifshay
• [libre-riscv-dev] [Libre-soc-bugs] [Bug 405] Write PowerPC64 backend for Cranelift   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 25jun2020   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 29jun2020   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 29jun2020   Jacob Lifshay
• [libre-riscv-dev] IBM releases A2I core VHDL   Jacob Lifshay
• [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder tables: M-Form and X-Form switched RS and RB   Paul Mackerras
• [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder tables: M-Form and X-Form switched RS and RB   Paul Mackerras
• [libre-riscv-dev] Contributing to the Libre-Soc Project   Sanjay Menon
• [libre-riscv-dev] Successful subscription   Sanjay Menon
• [libre-riscv-dev] Understanding the LibreSOC core   Sanjay Menon
• [libre-riscv-dev] Understanding the LibreSOC core   Sanjay Menon
• [libre-riscv-dev] daily kan-ban update 01jun2020   Michael Nolan
• [libre-riscv-dev] Understanding the LibreSOC core   Michael Nolan
• [libre-riscv-dev] Understanding the LibreSOC core   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 09jun2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 22jun2020   Michael Nolan
• [libre-riscv-dev] libresoc memory architecture   Michael Nolan
• [libre-riscv-dev] libresoc memory architecture   Michael Nolan
• [libre-riscv-dev] libresoc memory architecture   Michael Nolan
• [libre-riscv-dev] libresoc memory architecture   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 26jun2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 26jun2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 26jun2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 26jun2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 26jun2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 01jun2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 02jun2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 02jun2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 02jun2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 03jun2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 04jun2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 09jun2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 10jun2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 11jun2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 25jun2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 29jun2020   Tobias Platen
• [libre-riscv-dev] Introduction   Anais Poirier
• [libre-riscv-dev] daily kan-ban update 01jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 01jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 01jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 01jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 01jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 02jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 03jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 03jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 03jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 03jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 04jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 05jun2020   Cole Poirier
• [libre-riscv-dev] Request for input and technical expertise for =?utf-8?Q?Syst=C3=A8mes_?=Libres Amazon Alexa IOT Pitch 10-JUN-2020   Cole Poirier
• [libre-riscv-dev] "simple" core   Cole Poirier
• [libre-riscv-dev] "simple" core   Cole Poirier
• [libre-riscv-dev] "simple" core   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 08jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 08jun2020   Cole Poirier
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Cole Poirier
• [libre-riscv-dev] Request for input and technical expertise for =?utf-8?Q?Syst=C3=A8mes_?=Libres Amazon Alexa IOT Pitch 10-JUN-2020   Cole Poirier
• [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)   Cole Poirier
• [libre-riscv-dev] mortbopet/Ripes: A graphical processor simulator and assembly editor for the RISC-V ISA   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 09jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 09jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 09jun2020   Cole Poirier
• [libre-riscv-dev] Request for input and technical expertise for =?utf-8?Q?Syst=C3=A8mes_?=Libres Amazon Alexa IOT Pitch 10-JUN-2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 10jun2020   Cole Poirier
• [libre-riscv-dev] why developers love rust on stackoverflow blog   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 09jun2020   Cole Poirier
• [libre-riscv-dev] Fwd: programmerjake mentioned you in Intel Details Lakefield With Hybrid Technology   Cole Poirier
• [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)   Cole Poirier
• [libre-riscv-dev] Fall 2022 Interfaces   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 11jun2020   Cole Poirier
• [libre-riscv-dev] Fall 2022 Interfaces   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 12jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 12jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 12jun2020   Cole Poirier
• [libre-riscv-dev] 2pm UK time, 17 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Cole Poirier
• [libre-riscv-dev] 2pm UK time, 17 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Cole Poirier
• [libre-riscv-dev] Introduction   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 15jun2020   Cole Poirier
• [libre-riscv-dev] Introduction   Cole Poirier
• [libre-riscv-dev] Minerva L1 Cache   Cole Poirier
• [libre-riscv-dev] Minerva L1 Cache   Cole Poirier
• [libre-riscv-dev] Introduction   Cole Poirier
• [libre-riscv-dev] Introduction   Cole Poirier
• [libre-riscv-dev] *DAY MOVED* 2pm UK time, 18 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Cole Poirier
• [libre-riscv-dev] *DAY MOVED* 2pm UK time, 18 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Cole Poirier
• [libre-riscv-dev] Introduction   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 17jun2020   Cole Poirier
• [libre-riscv-dev] libre-soc exim4 wouldn't talk to gmail for 2-3 days   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 19jun2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 17jun2020   Cole Poirier
• [libre-riscv-dev] nMIgen now generates C++ models through yosysCXX!!!   Cole Poirier
• [libre-riscv-dev] Tests in soc/fu   Cole Poirier
• [libre-riscv-dev] Tests in soc/fu   Cole Poirier
• [libre-riscv-dev] Tests in soc/fu   Cole Poirier
• [libre-riscv-dev] renaming master branch   Cole Poirier
• [libre-riscv-dev] Tests in soc/fu   Cole Poirier
• [libre-riscv-dev] vulkan driver for broadcom videocore iv   Cole Poirier
• [libre-riscv-dev] Tests in soc/fu   Cole Poirier
• [libre-riscv-dev] Scoreboard and LDST questions   Cole Poirier
• [libre-riscv-dev] libre-soc exim4 wouldn't talk to gmail for 2-3 days   Cole Poirier
• [libre-riscv-dev] nMIgen now generates C++ models through yosysCXX!!!   Cole Poirier
• [libre-riscv-dev] nMIgen now generates C++ models through yosysCXX!!!   Cole Poirier
• [libre-riscv-dev] Very Subtle Synchronous nMigen Behavior   Cole Poirier
• [libre-riscv-dev] Tests in soc/fu   Cole Poirier
• [libre-riscv-dev] Scoreboard and LDST questions   Cole Poirier
• [libre-riscv-dev] libre-soc exim4 wouldn't talk to gmail for 2-3 days   Cole Poirier
• [libre-riscv-dev] Scoreboard and LDST questions   Cole Poirier
• [libre-riscv-dev] Scoreboard and LDST questions   Cole Poirier
• [libre-riscv-dev] Scoreboard and LDST questions   Cole Poirier
• [libre-riscv-dev] Scoreboard and LDST questions   Cole Poirier
• [libre-riscv-dev] Scoreboard and LDST questions   Cole Poirier
• [libre-riscv-dev] vulkan driver for broadcom videocore iv   Cole Poirier
• [libre-riscv-dev] vulkan driver for broadcom videocore iv   Cole Poirier
• [libre-riscv-dev] vulkan driver for broadcom videocore iv   Cole Poirier
• [libre-riscv-dev] mythic-beasts offered an upgrade for the virtual server behind libre-soc.org   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 11jun2020   Cesar Strauss
• [libre-riscv-dev] effects of powered-off chip sections on current leakage   Cesar Strauss
• [libre-riscv-dev] *DAY MOVED* 2pm UK time, 18 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Cesar Strauss
• [libre-riscv-dev] daily kan-ban update 22jun2020   Cesar Strauss
• [libre-riscv-dev] libresoc memory architecture   Cesar Strauss
• [libre-riscv-dev] Named Records in nMigen   Jock Tanner
• [libre-riscv-dev] NLNet018TV documentation   Staf Verhaegen
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Staf Verhaegen
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Staf Verhaegen
• [libre-riscv-dev] Introduction   Staf Verhaegen
• [libre-riscv-dev] Introduction   Staf Verhaegen
• [libre-riscv-dev] Introduction   Staf Verhaegen
• [libre-riscv-dev] daily kan-ban update 09jun2020   Alain D D Williams
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   Alain D D Williams
• [libre-riscv-dev] Tests in soc/fu   Alain D D Williams
• [libre-riscv-dev] Tests in soc/fu   Alain D D Williams
• [libre-riscv-dev] Tests in soc/fu   Alain D D Williams
• [libre-riscv-dev] Enabling Small images on the mailing list   Alain D D Williams
• [libre-riscv-dev] Intel Skylake QA "abnormally bad"   Alain D D Williams
• [libre-riscv-dev] Named Records in nMigen   Yehowshua
• [libre-riscv-dev] Named Records in nMigen   Yehowshua
• [libre-riscv-dev] Move FHDLTestCase to our utils folder   Yehowshua
• [libre-riscv-dev] Move FHDLTestCase to our utils folder   Yehowshua
• [libre-riscv-dev] daily kan-ban update 04jun2020   Yehowshua
• [libre-riscv-dev] daily kan-ban update 04jun2020   Yehowshua
• [libre-riscv-dev] publish crowdsupply update ourselves   Yehowshua
• [libre-riscv-dev] GPU Drivers ROCM   Yehowshua
• [libre-riscv-dev] Introduction and Questions   Yehowshua
• [libre-riscv-dev] Contributing to the Libre-Soc Project   Yehowshua
• [libre-riscv-dev] FHDLTestCase   Yehowshua
• [libre-riscv-dev] FHDLTestCase   Yehowshua
• [libre-riscv-dev] FHDLTestCase   Yehowshua
• [libre-riscv-dev] Scoreboard Tests   Yehowshua
• [libre-riscv-dev] "simple" core   Yehowshua
• [libre-riscv-dev] Using formal to expose bugs in scoreboard   Yehowshua
• [libre-riscv-dev] Using formal to expose bugs in scoreboard   Yehowshua
• [libre-riscv-dev] Understanding the LibreSOC core   Yehowshua
• [libre-riscv-dev] Understanding the LibreSOC core   Yehowshua
• [libre-riscv-dev] Understanding the LibreSOC core   Yehowshua
• [libre-riscv-dev] Understanding the LibreSOC core   Yehowshua
• [libre-riscv-dev] Understanding the LibreSOC core   Yehowshua
• [libre-riscv-dev] Understanding the LibreSOC core   Yehowshua
• [libre-riscv-dev] AMD ISAs   Yehowshua
• [libre-riscv-dev] AMD ISAs   Yehowshua
• [libre-riscv-dev] AMD ISAs   Yehowshua
• [libre-riscv-dev] AMD ISAs   Yehowshua
• [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020   Yehowshua
• [libre-riscv-dev] AMD ISAs   Yehowshua
• [libre-riscv-dev] LD/ST now a bit better. extra NLNet budgets   Yehowshua
• [libre-riscv-dev] Handling POWERVec Instructions   Yehowshua
• [libre-riscv-dev] Fall 2022 Interfaces   Yehowshua
• [libre-riscv-dev] Fall 2022 Interfaces   Yehowshua
• [libre-riscv-dev] Fall 2022 Interfaces   Yehowshua
• [libre-riscv-dev] Fall 2022 Interfaces   Yehowshua
• [libre-riscv-dev] Fall 2022 Interfaces   Yehowshua
• [libre-riscv-dev] Fall 2022 Interfaces   Yehowshua
• [libre-riscv-dev] Fall 2022 Interfaces   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] 2pm UK time, 17 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Yehowshua
• [libre-riscv-dev] 2pm UK time, 17 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] daily kan-ban update 15jun2020   Yehowshua
• [libre-riscv-dev] Introduction   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] Introduction   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] Introduction   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] Introduction   Yehowshua
• [libre-riscv-dev] Introduction   Yehowshua
• [libre-riscv-dev] Minerva L1 Cache   Yehowshua
• [libre-riscv-dev] Yehowshua Tasks   Yehowshua
• [libre-riscv-dev] Yehowshua Tasks   Yehowshua
• [libre-riscv-dev] *DAY MOVED* 2pm UK time, 18 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Yehowshua
• [libre-riscv-dev] daily kan-ban update 16jun2020   Yehowshua
• [libre-riscv-dev] Yehowshua Tasks   Yehowshua
• [libre-riscv-dev] Yehowshua Tasks   Yehowshua
• [libre-riscv-dev] Enabling Small images on the mailing list   Yehowshua
• [libre-riscv-dev] Yehowshua Tasks   Yehowshua
• [libre-riscv-dev] Yehowshua Tasks   Yehowshua
• [libre-riscv-dev] Very Subtle Synchronous nMigen Behavior   Yehowshua
• [libre-riscv-dev] daily kan-ban update 17jun2020   Yehowshua
• [libre-riscv-dev] *DAY MOVED* 2pm UK time, 18 Jun 2020: Marketnext hackathon preliminary setup and introduction call   Yehowshua
• [libre-riscv-dev] Very Subtle Synchronous nMigen Behavior   Yehowshua
• [libre-riscv-dev] Very Subtle Synchronous nMigen Behavior   Yehowshua
• [libre-riscv-dev] Very Subtle Synchronous nMigen Behavior   Yehowshua
• [libre-riscv-dev] Enabling Small images on the mailing list   Yehowshua
• [libre-riscv-dev] daily kan-ban update 17jun2020   Yehowshua
• [libre-riscv-dev] Yehowshua Tasks   Yehowshua
• [libre-riscv-dev] nMIgen now generates C++ models through yosysCXX!!!   Yehowshua
• [libre-riscv-dev] Tests in soc/fu   Yehowshua
• [libre-riscv-dev] daily kan-ban update 17jun2020   Yehowshua
• [libre-riscv-dev] Yehowshua Tasks   Yehowshua
• [libre-riscv-dev] Fwd: nMigen meetings   Yehowshua
• [libre-riscv-dev] Scoreboard and LDST questions   Yehowshua
• [libre-riscv-dev] Scoreboard and LDST questions   Yehowshua
• [libre-riscv-dev] renaming master branch   Yehowshua
• [libre-riscv-dev] vulkan driver for broadcom videocore iv   Yehowshua
• [libre-riscv-dev] nMIgen now generates C++ models through yosysCXX!!!   Yehowshua
• [libre-riscv-dev] https://slashdot.org/story/20/06/23/1548205/amazon-unveils-2-billion-fund-to-invest-in-startups-building-sustainable-technology   Yehowshua
• [libre-riscv-dev] https://slashdot.org/story/20/06/23/1548205/amazon-unveils-2-billion-fund-to-invest-in-startups-building-sustainable-technology   Yehowshua
• [libre-riscv-dev] https://slashdot.org/story/20/06/23/1548205/amazon-unveils-2-billion-fund-to-invest-in-startups-building-sustainable-technology   Yehowshua
• [libre-riscv-dev] daily kan-ban update 28jun2020   Yehowshua
• [libre-riscv-dev] IBM releases A2I core VHDL   Yehowshua
• [libre-riscv-dev] ASIC layout questions   whygee at f-cpu.org
• [libre-riscv-dev] IBM releases A2I core VHDL   whygee at f-cpu.org
• [libre-riscv-dev] IBM releases A2I core VHDL   whygee at f-cpu.org
• [libre-riscv-dev] 130nm for the hackers : finally a reality ?   whygee at f-cpu.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 360] New: move RS to 1st or 2nd operand in CSV files   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 300] Documentation for the SOC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 360] move RS to 1st or 2nd operand in CSV files   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 358] new MCU-ALU test picked up RC / OE / CR handling issue   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 361] New: all test_pipe_caller.py needs RA=0 tests   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 362] New: improvements to nmigen and yosys   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 175] NLNet 2019 Wishbone proposal 2019-10-043   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 362] improvements to nmigen and yosys   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] New: inconsistency between isel and mfcr unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 274] Investigate how BSV performs Formal Verification and what can be Applied to FPUs   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 274] Investigate how BSV performs Formal Verification and what can be Applied to FPUs   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 274] Investigate how BSV performs Formal Verification and what can be Applied to FPUs   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 364] New: Python YosysCXX Interface   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 364] Python YosysCXX Interface   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 364] CXXRTL Python Interface   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 362] improvements to nmigen and yosys   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] New: ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 364] CXXRTL Python Interface   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 364] CXXRTL Python Interface   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 364] CXXRTL Python Interface   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 364] CXXRTL Python Interface   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 366] New: Create new buzilla product "Systemes Libres Organization"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 367] New: Setup weekly 30 min organizational video call like OPF Virtual Coffee Calls   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 366] Create new buzilla product "Systemes Libres Organization"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 366] Create new buzilla product "Systemes Libres Organization"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 364] CXXRTL Python Interface   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 364] CXXRTL Python Interface   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 364] CXXRTL Python Interface   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 360] move RS to 1st or 2nd operand in CSV files   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 368] New: Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 366] Create new buzilla product "Systemes Libres Organization"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 366] Create new buzilla product "Systemes Libres Organization"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 369] New: missing XER SO/OV/32 check in test_pipe_caller.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 197] Formal correctness proof needed of the 6600-style Out-of-Order execution engine   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 81] implement 6600-style "precise" out-of-order scoreboard   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 370] New: need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 371] New: code removed by commit 12297566322355ce5fed2e2a5460bea54f69e79e   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 371] code removed by commit 12297566322355ce5fed2e2a5460bea54f69e79e   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 371] code removed by commit 12297566322355ce5fed2e2a5460bea54f69e79e   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 371] code removed by commit 12297566322355ce5fed2e2a5460bea54f69e79e   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 371] code removed by commit 12297566322355ce5fed2e2a5460bea54f69e79e   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 371] code removed by commit 12297566322355ce5fed2e2a5460bea54f69e79e   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 372] New: create cycle-accurate JIT-compiler-based processor simulator   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 361] all test_pipe_caller.py needs RA=0 tests   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 371] code removed by commit 12297566322355ce5fed2e2a5460bea54f69e79e   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 371] code removed by commit 12297566322355ce5fed2e2a5460bea54f69e79e   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 371] code removed by commit 12297566322355ce5fed2e2a5460bea54f69e79e   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 371] code removed by commit 12297566322355ce5fed2e2a5460bea54f69e79e   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 373] New: Investigate the possibility of implementing parts of OPENCAPI to supplement Wisbone vB4   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] New: add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 375] New: Finding new project members who can help with complex detailed work such as LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 375] Finding new project members who can help with complex detailed work such as LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 374] add repo on github that points to git.libre-soc.org as a way to increase searchability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] New: Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 375] Finding new project members who can help with complex detailed work such as LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 377] New: possible bug in Simulator Mem ld/st function   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 377] possible bug in Simulator Mem ld/st function   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 378] New: Additional project management infrastructure   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 377] possible bug in Simulator Mem ld/st function   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 379] New: Create wiki page for recruitment letter to Universities (& etc.) to point to   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 379] Create wiki page for recruitment letter to Universities (& etc.) to point to   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 379] Create wiki page for recruitment letter to Universities (& etc.) to point to   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 379] Create wiki page for recruitment letter to Universities (& etc.) to point to   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 379] Create wiki page for recruitment letter to Universities (& etc.) to point to   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 379] Create wiki page for recruitment letter to Universities (& etc.) to point to   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 381] New: update algebraics for num-bigint v0.3   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 377] possible bug in Simulator Mem ld/st function   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 377] possible bug in Simulator Mem ld/st function   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 377] possible bug in Simulator Mem ld/st function   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 382] New: nmigen wishbone Memory object needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 383] New: Complete first functional POWER9 Core   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 383] Complete first functional POWER9 Core   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 384] New: Documentation for the POWER9 Core and internal architecture   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 384] Documentation for the POWER9 Core and internal architecture   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 175] NLNet 2019 Wishbone proposal 2019-10-043   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 382] nmigen wishbone Memory object needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 382] nmigen wishbone Memory object needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 375] Finding new project members who can help with complex detailed work such as LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 385] New: ReservationStations MultiCompUnit unit test needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 385] ReservationStations MultiCompUnit unit test needed   bugzilla-daemon at libre-soc.org

Last message date: Tue Jun 30 19:43:49 BST 2020
Archived on: Tue Jun 30 19:44:14 BST 2020

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