[libre-riscv-dev] effects of powered-off chip sections on current leakage

[Cesar Strauss]

Em 14/06/2020 17:07, Jacob Lifshay escreveu:
> On Sun, Jun 14, 2020, 04:31 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>> ok so if there's an actual MOSFET that cuts power to those planes,
>> there's nothing to "resist", so the idea that you came up with of
>> cutting power entirely has merit that needs a proper investigation.
> 
> 
> After a little looking around, I didn't see anything that unambiguously
> stated that turning off the power planes will reduce leakage power, however
> basically everyone I found seemed to imply that.
> 
> https://en.wikipedia.org/wiki/Power_gating

Remember also to isolate any inputs, otherwise they will tend to power
the core, and generally create a load on the line.

Happened to me the other day.

I have two board connected by I2C. I power down just one, and the power
led stays on. Power off the other instead, and the I2C bus on the first
becomes unusable.

Regards,

Cesar