[libre-riscv-dev] effects of powered-off chip sections on current leakage

[Jacob Lifshay]

On Sun, Jun 14, 2020, 04:31 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Sun, Jun 14, 2020 at 6:06 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > Please explain in more detail, perhaps with some supporting references --
> > it still makes close to zero sense to me how additional unused silicon
> area
> > could affect the rest of the chip, since that area itself couldn't be
> > drawing any power since all wires into it that are at 0V due to the power
> > rails and I/O signals being switched off.
>
> beyond the fact that it occurs, i do not know the details.  i had a
> mentor who explained it to me, and (in the case of the GPS
> correlators) a second person confirmed it.
>
> it is something to do with the fact that a transistor is not a perfect
> isolator, and that it is both a resistor and a capacitor.  the
> resistance, when there is zero power applied to the Drain, is
> extremely small but it is *not* zero, between the two planes that are
>

assuming you meant resistance is extremely large but not infinity.
extremely small means a very large current would flow.

directly above and below the transistor (one VDD - +ve voltage, one
> VSS - GND)
>

from what I understand, the leakage current is mostly caused by a
combination of gate and other insulator defects, quantum tunneling, and
minority carriers. Those basically act as a resistor between the source,
drain, and gate.

If the block is not switching, we can ignore any capacitive effects since
the capacitors won't be charging or discharging.

We will probably want a separate clock and reset domain for each power
domain.


> ok so if there's an actual MOSFET that cuts power to those planes,
> there's nothing to "resist", so the idea that you came up with of
> cutting power entirely has merit that needs a proper investigation.


After a little looking around, I didn't see anything that unambiguously
stated that turning off the power planes will reduce leakage power, however
basically everyone I found seemed to imply that.

https://en.wikipedia.org/wiki/Power_gating

Jacob