[libre-riscv-dev] effects of powered-off chip sections on current leakage
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jun 14 12:30:21 BST 2020
On Sun, Jun 14, 2020 at 6:06 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> Please explain in more detail, perhaps with some supporting references --
> it still makes close to zero sense to me how additional unused silicon area
> could affect the rest of the chip, since that area itself couldn't be
> drawing any power since all wires into it that are at 0V due to the power
> rails and I/O signals being switched off.
beyond the fact that it occurs, i do not know the details. i had a
mentor who explained it to me, and (in the case of the GPS
correlators) a second person confirmed it.
it is something to do with the fact that a transistor is not a perfect
isolator, and that it is both a resistor and a capacitor. the
resistance, when there is zero power applied to the Drain, is
extremely small but it is *not* zero, between the two planes that are
directly above and below the transistor (one VDD - +ve voltage, one
VSS - GND)
ok so if there's an actual MOSFET that cuts power to those planes,
there's nothing to "resist", so the idea that you came up with of
cutting power entirely has merit that needs a proper investigation.
> neat! didn't know about A-GPS before, though I assumed it was related to
> GPS somehow.
there was a company that "invented" the concept around 2006, it's a
logical progression. if you have a LAT/LON already to within a few
miles, the search space is clearly going to be far smaller.
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