[libre-riscv-dev] ASIC layout questions

whygee at f-cpu.org whygee at f-cpu.org
Thu Jun 25 18:02:31 BST 2020

On 2020-06-25 13:49, Luke Kenneth Casson Leighton wrote:
> one thing: all the regfiles need to be write-through.  i.e. if there
> is one port that is writing and another port is simultaneously reading
> to that same register, the data being written *must* be passed through
> to the reader... *on that clock cycle*.  in the regfile.py code i have
> done this with a "wrapper" on the front of the nmigen Memory class.

you mean : it's a transparent latch, which takes 1/2 the size
of a edge-triggered flip-flop.

If the timing is too tight for the data signal to go all the way
through the array of latches, you can AND the unary read and write
signals to trigger a MUX at the output (which I suppose you did in
the wrapper).

> l.

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