[libre-riscv-dev] ASIC layout questions

[Luke Kenneth Casson Leighton]

On Thu, Jun 25, 2020 at 6:02 PM <whygee at f-cpu.org> wrote:

> If the timing is too tight for the data signal to go all the way
> through the array of latches, you can AND the unary read and write
> signals to trigger a MUX at the output (which I suppose you did in
> the wrapper).

yes, basically, that's what i did.  with all of the register
"addresses" being unary, it's easy to do.  for the binary versions
it's harder to do because you have to decode the binary reg numbers to
unary first *or* perform an O(N*M) array of binary-address
comparators, N=read_ports, M=write_ports.

l.