[libre-riscv-dev] Yehowshua Tasks

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jun 19 02:51:38 BST 2020

On Fri, Jun 19, 2020 at 1:14 AM Yehowshua <yimmanuel3 at gatech.edu> wrote:

> Yeah - I don’t think that `CachedLoadStoreUnit` is quite what you want.
> It’s basically the memory stage in the 6 stage minerva pipeline.


> Its a wrapper around the cache.

yyup.  perfect.

see follow-up message.  it becomes clear what's needed once you ignore
the self.dbus part of LSUI and focus exclusively on the x_* and m_*
interaction.  a code-morph where the TestMemory of L0CacheBuffer is
moved behind a LoadStoreUnitInterface (which completely ignores the
wishbone bus record) helps to make it clear.


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