[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #53 from Cesar Strauss <cestrauss at gmail.com> ---
commit 71a791cf5f05bd5858fdc60f4ccdca936edc1d75
Author: Cesar Strauss <cestrauss at gmail.com>
Date:   Sun Jun 7 16:32:11 2020 -0300

    Make the test ALU conform to the valid/ready protocol

    Adjust the test case accordingly.

It was definitively not a one-line change. But it was fun.

Select any other operation than MUL, ADD, or SHR, and it will do a
combinatorial subtraction, with zero-delay and no registering.

The interesting thing about zero-delay is that, due to the absence of an
internal register, it will not release the input data until the result is
transferred out.

Basically, the handshake signals of the input and output ports are directly
connected between them, only the data is modified between the ports.

Nice change, working with RTL again. Will go back to the parallel unit tests,
now.

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