[libre-riscv-dev] Fall 2022 Interfaces

[Cole Poirier]

> On Jun 11, 2020, at 9:01 PM, Jacob Lifshay <programmerjake at gmail.com> wrote:
> 
> On Thu, Jun 11, 2020, 19:59 Yehowshua <yimmanuel3 at gatech.edu> wrote:
> 
>> Was talking with Pine64 and Raptor about Fall2022 interfaces which I’m
>> trying to finalize.
>> We need 10rx and 14tx SERDES.
>> 4rx and 4tx for the OMI will need to run at 25GHz for DDR4 over OMI.
>> 
> 
> 25GHz seems *really* fast, probably impractically so unless going to *lots*
> of effort, did you mean 2.5GHz?

Maybe 25GB/s? “The OMI DDR4 Differential DIMM memory module supports a data throughput rate of 25.6GB/s with a latency of 40ns and densities up to 256GB. The new 84-pin DDR4 DDIMM is intended for use in standard server environments, using a serial interface and a differential Data Buffer (dDB) from Microchip. The DDIMM supports IBM’s P9 AIO and P10 processors’ memory attached architecture. The P9 AIO and P10 memory bus is defined with one read port and one write port per channel, each having eight unidirectional differential lanes supporting 25.6 Gbps data rate over the OMI direct attached to the DDIMM.”
https://www.eenewseurope.com/news/ddr4-differential-dimm-grows-opencapi-ecosystem

Still that’s for power 10 and late generation power 9 server processors.

Cole