[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=313

--- Comment #49 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #48)
> (In reply to Luke Kenneth Casson Leighton from comment #44)
> 
> > yes.  it's accessed often enough.
> 
> Lol, back when I was doing some PowerPC reverse engineering I never saw a
> bctar.

okok :)  put another way: i don't want the hassle of adding an extra regfile
port (a slow SPR one) to the branch regspecs :)

> > then, read_fast1 and read_fast2 can be used in both unit tests:
> > fu/compunit/test/test_branch_compunit.py
> > and
> > fu/branch/test/test_pipe_caller.py
> 
> This has been done to test_pipe_caller, still need to do the compunit one.

the compunit one _should_ just pick it up automatically, because of the use
of regspecs.

howeverrrr.... there's something fishy going on in test_bc_cr, which
is only noticed on the *next* instruction, test_bc_ctr

here's test_bc_cr output phase:

check extra output 'bc 12, 3, -12720' {}  <-- uh-oh... no output regs.


test_bc_ctr


following that, this - in the output log - is extremely bad:

before inputs, rd_rel, wr_rel:  0b1100 0b101 <--- wr_rel *must* be zero here.
rd_rel 0 wait HI 0 spr1 0x57b4136e
rd_rel 0 wait HI 1 spr1 0x57b4136e
rd_rel 2 wait HI 1 cr_a 0x0
rd_rel 3 wait HI 1 cia 0x0

if that occurs, it means that the pipeline has set Data.ok flags but that
PowerDecode2 has *NOT* set the corresponding write regs information.

or the other way round.

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