[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Jun 7 21:25:20 BST 2020


--- Comment #9 from Michael Nolan <mtnolan2640 at gmail.com> ---
GRR. I believe at some point I used the fields directly generated from
power_fields.py (fields_x['BF'] or something like that), which needed the
[0:-1]. But since it got changed to use the signals from the decoder, the
[0:-1] chopped off the top bit. I think I fixed another error in the decoder
just like that recently, I probably should have gone through and made sure
there weren't any like it.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list