[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=363

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|CONFIRMED                   |RESOLVED
         Resolution|---                         |FIXED

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
michael i've just been investigating by adding extra unit tests that
i believe to be reasonable:

    def test_1_mcrf(self):
        for i in range(20):
            src = random.randint(0, 7)
            dst = random.randint(0, 7)
            lst = [f"mcrf {src}, {dst}"]
            cr = random.randint(0, (1<<32)-1)
        self.run_tst_program(Program(lst), initial_cr=cr)

    def test_0_mcrf(self):
        for i in range(8):
            lst = [f"mcrf 5, {i}"]
            cr = 0xfeff0001
            self.run_tst_program(Program(lst), initial_cr=cr)

(i used numbering to get them to run first)

test_0_mcrf one fails straight away (even on the first loop):
    self.assertEqual(expected_cr, real_cr, code)
AssertionError: 14 != 15 : mcrf 5, 0

a clue is here:


    def op_mcrf(self, CR):
        print ("op_mcrf", hex(CR.si.value), "BF", BF, "BFA", BFA)
        CR.si[(4 * BF) + 32:(4 * BF) + 35 + 1] = CR.si[(4 * BFA) + 32:(4 * BFA)
+ 35 + 1]
        print ("op_mcrf", hex(CR.si.value))


this prints out:

op_mcrf 0xfeff0001 BF 5 BFA 0
op_mcrf 0xfeff0f01

and... oink, the write_cr is invalid.  it's set to 1.

            cr_sel = yield dec2.e.write_cr.data
            expected_cr = simulator.cr.get_range().value
            print(f"CR whole: {expected_cr:x}, sel {cr_sel}")

CR whole: feff0f01, sel 1

ah HA!

--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -445,7 +445,7 @@ class DecodeCROut(Elaboratable):
                 comb += self.cr_bitfield.data.eq(0)
                 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
             with m.Case(CROutSel.BF):
-                comb += self.cr_bitfield.data.eq(self.dec.FormX.BF[0:-1])
+                comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
                 comb += self.cr_bitfield.ok.eq(1)
             with m.Case(CROutSel.BT):

that's it!  that's all it was.  what a pain.

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