[libre-riscv-dev] daily kan-ban update 05jun2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jun 5 19:53:06 BST 2020


* got surprisingly far very quickly with the unit test for the simple
core.  all integer comparisons of the regfile work fine.
* worked with Cole on the TRAP pipeline. there is oddness in microwatt from
SPRs being passed through reg data lines, had to sort that out


* slept for several hours. very long day yesterday.
* tried tracking down Condition Register discrepancies in the read/write
side to CR regfile. related to bit ordering.
* go over LDST buffer to be able to help Tobias.
* start thinking how to pull in LDSTCompUnit into the pipeline tests.

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

More information about the libre-riscv-dev mailing list