[libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=55

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #4)
> I want to add that also DDR signaling is left to be implemented in the logic
> circuit on top of the level-shifted core output. It typically is done by
> using both a rising edge and a falling edge triggered flip-flop on this
> output.

this is fantastic, staf.  look forward to hearing how the test goes.

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