[libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=55

--- Comment #4 from Staf Verhaegen <staf at fibraservi.eu> ---
I want to add that also DDR signaling is left to be implemented in the logic
circuit on top of the level-shifted core output. It typically is done by using
both a rising edge and a falling edge triggered flip-flop on this output.

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