[libre-riscv-dev] IBM releases A2I core VHDL

[whygee at f-cpu.org]

On 2020-06-30 11:27, Luke Kenneth Casson Leighton wrote:
> On Tue, Jun 30, 2020 at 10:06 AM Jacob Lifshay 
> <programmerjake at gmail.com> wrote:
>> Another option is that what they published is the output of a 
>> synthesizer.
> a synthesiser would not take care in doing this kind of thing:
> u_shd04_0: shd04_0_b(0 to 63) <= not( ( lftx04_0_bus(0 to 63) and 
> rolx04_0(0
> to 63) ) or ( lftx04_1_bus(0 to 63) and rolx04_1(0 to 63) ) );
> ( lftx04_1_bus(0 to 63) and rolx04_1(0 to 63) ) );
but then at the end of the file, why not use the vector notation
and/or an even smaller For... generate... blocks ?
that file is a big "fuck you" statement.

> l.
yg