[libre-riscv-dev] Fwd: [Git][vlsi-eda/coriolis][devel] The VST driver may suppress linkage type.

Thu Jun 25 10:25:00 BST 2020

jean-paul, can i ask, does this happen to fix the issue of non-flattened
FPMUL64 layout using alliance?

l.

---------- Forwarded message ----------
From: *Jean-Paul Chaput* <gitlab at gitlab.lip6.fr>
Date: Thursday, June 25, 2020
Subject: [Git][vlsi-eda/coriolis][devel] The VST driver may suppress
linkage type.
To: coriolis-cvs at soc.lip6.fr

Jean-Paul Chaput pushed to branch devel at Coriolis VLSI EDA / Coriolis
<https://gitlab.lip6.fr/vlsi-eda/coriolis> Commits:

   - *b23f620c
   <https://gitlab.lip6.fr/vlsi-eda/coriolis/-/commit/b23f620c5d57df01ce4463603ffdb2ae58c9ad37>*
   by Jean-Paul Chaput *at 2020-06-24T23:27:21+02:00*

   The VST driver may suppress linkage type.

   * Change: In Vhdl:::Signal::toVhdlPort(), in Alliance VST signal with
       undefined directions are typed "linkage". This may not be compatible
       with vasy, so allow to replace them by "in".
   * New: In CRL::Catalog::State, add a new flag VstNoLinkage to tell if
      the VST driver should not use the "linkage" type.
   * Change: In Vhdl::Entity, add a VstNoLinkage flag to disable the use
       of the "linkage" type.

6 changed files:

   - crlcore/src/ccore/alliance/vst/VhdlEntity.cpp
   <https://gitlab.lip6.fr/vlsi-eda/coriolis/-/commit/b23f620c5d57df01ce4463603ffdb2ae58c9ad37#f31ced88ed94c1278bb768360eef91818997b8fb>
   - crlcore/src/ccore/alliance/vst/VhdlSignal.cpp
   <https://gitlab.lip6.fr/vlsi-eda/coriolis/-/commit/b23f620c5d57df01ce4463603ffdb2ae58c9ad37#f8cfd9411ed6ff2b9d799b686d0e7b91e23a43c5>
   - crlcore/src/ccore/alliance/vst/VstDriver.cpp
   <https://gitlab.lip6.fr/vlsi-eda/coriolis/-/commit/b23f620c5d57df01ce4463603ffdb2ae58c9ad37#f00c33cc4be9e27412bb2e20401b00c66ebe42a6>
   - crlcore/src/ccore/crlcore/Catalog.h
   <https://gitlab.lip6.fr/vlsi-eda/coriolis/-/commit/b23f620c5d57df01ce4463603ffdb2ae58c9ad37#49b55d53d6047791ded3017492d0e921a1df4f73>
   - crlcore/src/ccore/crlcore/VhdlEntity.h
   <https://gitlab.lip6.fr/vlsi-eda/coriolis/-/commit/b23f620c5d57df01ce4463603ffdb2ae58c9ad37#6acc750b4ee1034bf1f269838d587a311452a0b9>
   - crlcore/src/pyCRL/PyCatalogState.cpp
   <https://gitlab.lip6.fr/vlsi-eda/coriolis/-/commit/b23f620c5d57df01ce4463603ffdb2ae58c9ad37#c64b422433577477620d8e9d55af6640a8055ae9>

—
View it on GitLab
<https://gitlab.lip6.fr/vlsi-eda/coriolis/-/commit/b23f620c5d57df01ce4463603ffdb2ae58c9ad37>.

You're receiving this email because of your account on gitlab.lip6.fr. If
you'd like to receive fewer emails, you can adjust your notification
settings.

-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68