[libre-riscv-dev] [Git][vlsi-eda/coriolis][devel] The VST driver may suppress linkage type.

[Luke Kenneth Casson Leighton]

On Thu, Jun 25, 2020 at 11:02 AM Jean-Paul Chaput
<Jean-Paul.Chaput at lip6.fr> wrote:
>
>
> errr... Yes you can. But I totally forgot what the problem was...

:)

> Can you gently remind me, I will look into it today.

you remember that we had some signals which were not connected to
anything?  and when alliance turned the BLIF into simplified-VHDL, it
assumed that *all* signals were connected?

therefore sometimes it would try to substitute VSS and sometimes VDD
but the missing signals would result in the ports being the wrong
length?

you managed to come up with a solution however i believe that because
of the complexity and size of FPMUL64, you may have missed a
corner-case.

consequently, the FPMUL64 experiment (soclayout/experiment6 or 7 i
think) fails with an error unless "flatten" is enabled.


> By the way, just to keep you posted on what I do:
>
> * I started some test with "test_issuer", and "started" is the right word.

:)

>   As a first try I'm going head on with the tools, it started yesterday
>   morning and progressing. The placement is ongoing, and may take about
>   a week...

noow you know why i suggested the hierarchical approach! :)

> Yosys gives a 850K gates design, which is huge, and inline
>   with those processing times.

woo!  that's 8 times larger than anything previously considered.  one
reason for it *might* be because the high-speed register files are
multi-port write.  there are only 8 entries however they are 64-bit
wide

>     I will also try a "block" approach. From the netlist structure I
>   can guess the general idea of the design (I think I recognize the
>   various units). But if you can provide an overall map, that would
>   be great (or a coarse grained schematic at unit level).

will do.  in the meantime: if you do a quick peek around with yosys
"show top" followed by "show thing" you'll get a pretty good idea.  i
*very deliberately* created simple hierarchies (classes) where there
is *not* a massive amount in each class, so each yosys "show" page
_should_ contain only a few objects.

> * In parallel, I'm looking for a bug in the generated VST (fast2
>   end up unconnected at core level).

whoops.

> This is a VST bug, but don't
>   occur on smaller designs so my "debug cycle" is long.

ok.

> * And lastly, I'm rewriting the "block" placer to manage more than
>   one clock tree and the high fanout net synthesis (those features
>   relies on a common framework). In collaboration with Staf.

nice

> * We are also in touch with Tim Ansell about the Skywater open PDK.

gooood.

>   To me, it's the first wedge in the NDA policy. And for an Academic,
>   it would be great because we can finally make direct comparison of
>   tools on the exact same real node.

hurrah.