[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #57 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #53)
> two things (on this bugreport):
> 
> 1) make a test_pipe_caller.py and remaining data structures/code. 
> (cookie-cut an existing one, delete all the switch statements).  don't
> overwrite pipe_data.py.  do cookie-cut a trap_input_data.py
> (cr_input_record.py)

This is done. Should I start trying to figure out how to write these unit tests
using fu/cr/test/test_pipe_caller as a guide? Or if this will be outside of my
current capacity, should I move on to bug #348?

> 2) add the pseudocode to sprset.mdwn (yes sprset.mdwn is a bad name) from
> comment #47
> 
> https://libre-soc.org/openpower/isa/sprset/

Waiting on your help with this one, I figured I shouldn't waste more time on it
given that it's likely something that you're capable of identifying and fixing
in a matter of seconds because you understand the parser completely.

> or if you're bored of this one for a while, move on to
> https://bugs.libre-soc.org/show_bug.cgi?id=348

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