[libre-riscv-dev] [Bug 377] New: possible bug in Simulator Mem ld/st function

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Jun 12 15:58:35 BST 2020


            Bug ID: 377
           Summary: possible bug in Simulator Mem ld/st function
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

michael, hi,

it looks like there might be a bug in caller.py Mem ld/st.  by accident
i asked a byte-store (stb) to write to address 0x9.  the memory-dump
(fu/compunits/test/test_compunit.py) dumps out the internal dictionary
(sim.mem.mem.items()) however it uses sim.mem.ld to initialise the
nmigen Memory object.

* bytes per word is 8
* address 9 divided by 8 is 1
* remainder is also 1.

does this mean that the LD/ST is being word-order realigned?

Writing 0xee to ST 0x9 memaddr 0x1/1
width,rem,shift,mask 1 1 0x30 0xff
mem @ 0x1: 0xabeeef0187654321
carry already done? 0b0
get_cu_outputs 2 0
after got outputs, rd_rel, wr_rel, wrmask:  0b0 0b0 0b0
busy 1
busy 1
busy 1
busy 0
check cu outputs stb 3, 1(2) {}
check extra output 'stb 3, 1(2)' 0 0
sim mem dump
         0 5432123412345678
         1 abeeef0187654321
         4 1828384822324252
nmigen mem dump
         0 5432123412345678
         1 abcdef018765ee21
         2 0000000000000000
         3 0000000000000000
         4 1828384822324252
         5 0000000000000000

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