[libre-riscv-dev] daily kan-ban update 15jun2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Jun 15 20:58:53 BST 2020

On Mon, Jun 15, 2020 at 4:11 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> * look at why the 2nd LD/ST instruction remains "busy" in test_core.py
> where in the test_ldst_compunit.py it is fine

found it quickly.  turns out that you must not link signals together
*after* you create a nmigen Simulator instance.  the nmigen
Simulator(m) instance must be the last thing done.

now the LD/ST unit tests also work in test_core.py as well.  this is a
significant step because with LD/ST, branch, and add (etc.) all
confirmed working, simple loops can be created once we have
instruction read/feed in place.

> * if that's found quickly, continue investigating the next step which
> is to first add in an instruction "reader" (I-Cache path) and second
> to point the PC at it and actually get instructions from an actual
> I-Cache / SRAM.

this is now the next high priority task: getting an SRAM that's on the
other side of a wishbone bus operational (and properly unit tested)
then dropping it into place on the L0CacheBuffer.

on a separate path an instruction queue can also be added... however
agaaain, that needs to be reading from a Memory, preferably via a
wishbone interface.

what i might do for now is just drop in a small SRAM just to get
something working.


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