[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Jun 5 14:39:32 BST 2020


--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
p34 section 2.4.1 of spec

Instructions are provided to perform logical operations on individual CR bits
and to test individual CR bits.
For all fixed-point instructions in which Rc=1, and for addic., andi., and
andis., the first three bits of CR Field 0 (bits 32:34 of the Condition
Register) are set by signed comparison of the result to zero, and the fourth
bit of CR Field 0 (bit 35 of the Condition Register) is copied from the SO
field of the XER. “Result” here refers to the entire 64-bit value placed into
the target register in 64-bit mode, and to bits 32:63 of the 64-bit value
placed into the target register in 32-bit mode.

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