[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #64 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #62)
> > Or is this  the one that is
> > generated from parsing the csv files?
> 
> yes.  hence the need for the pseudocode.  until that exists there *is* no
> mfmsr (etc) to test against!
> 
> in this case even the TRAP function has to be written.
> 
> this would (in python) move the SPRs about, set NIA to 0x700 blah blah.

This makes so much sense now and is very, very cool! Especially in light of
your comments from comment #59 "actually i don't [completely understand
pywriter.py]: it has been several months, and i wrote it very fast,
to perform a minimal job!"

Regarding your comment on today's kanban daily update, "put a preliminary
version of mtmsr into the mdwn for Cole to check", how do I go about checking
the mdwn pseudo code with the emulator and the nmigen module?

> the syntax is python-indented (that was a pig to implement), and borrowed
> python concepts such as brackets.  i replaced operators such as = with <-
> and so on.
> 
> subscripted ranges were obviously not possible to do in ASCII so i did
> straight brackets python slices but kept the POWER numbering.
> 
> so the translator pushes an extra +1 out on the "end" of the slice.
> 
> you saw that when doing bperm.

Thanks this helps me understand the 'problem' even better than I did from your
earlier comments. Also very ingenious.

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