[libre-riscv-dev] daily kan-ban update 15jun2020

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Mon, Jun 15, 2020 at 9:04 PM Yehowshua <yimmanuel3 at gatech.edu> wrote:
>
> >
> > what i might do for now is just drop in a small SRAM just to get
> > something working.
>
> You might already know, but you can do an SRAM like so:

yes - been using that as part of a semi-integrated thing in TstL0CacheBuffer:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/l0_cache.py;hb=HEAD#l507

which in turn uses TestMemory:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/testmem.py;hb=HEAD

which in turn uses nmigen Memory

l.