[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Jun 7 22:18:35 BST 2020


--- Comment #81 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #80)
> (In reply to Cole Poirier from comment #79)
> > This is our autogenerated from parsing csv files emulator? 
> nono, that's actually the function that gets called *by* the emulator.
> it's decoder/isa/caller.py (which is the base class for the simulator)
> > Is this something I can help with 
> actually, probably yes.  it should be as brain-dead simple as
> putting things into the self.spr dict:
>     self.spr['SRR0'] = self.pc.CIA
> and also modify the NIA.  that sort of thing.
> > So is this TRAP function added in sort of ad hoc via caller.py, because it
> > isn't contained in fixedtrap.mdwn?
> it is... however look at the PDF SPEC (or see comment #1 which contains
> the pseudo-code.  that's not a function, is it?

No indeed it seems more similar to a keyword. Ah, so just translating that
psuedo code into the TRAP method of ISACaller?

> so what i did was, identify the keyword "TRAP" and got it to output
> a *function* call "self.TRAP()".  auto-generated decoder/isa/fixedtrap.py
> now contains this:
> class fixedtrap:
>     @inject()
>     def op_twi(self, RA):
>         a = EXTS(RA[32:64])
>         if lt(a, EXTS(SI)) & TO[0]:self.TRAP()
>         if gt(a, EXTS(SI)) & TO[1]:self.TRAP()
> *now* it can call the function which was added in caller.py, *now* we
> can get that function to make the required modifications to the SPRs
> and to the PC (NIA - Next Instruction Address).

Aha, this is actually starting to make A LOT of sense :)

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