[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Jun 7 22:23:07 BST 2020


https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #82 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #79)
> (In reply to Luke Kenneth Casson Leighton from comment #75)

> > the normal solution for this is to "call in" something that *is* known,
> > and that would be the qemu emulator.  except we kinda need some help from
> > michael to do that in a short timescale, or we need to investigate it
> > in a longer one.  given that there's a critical task needed (investigating
> > the CR bit-ordering) i'd rather we not pull him off of that.
> 
> So until we have the known qemu emulator I should just try writing
> appropriate unit tests for when we have the emulator working? Should I raise
> a bug report for investigating the qemu powerpc emulator on a longer
> timescale?

yes please.

> What should I say in the bug description?

that we need one example unit test of how to run some assembly code
"qemu vs simulator" rather than "qemu vs hardware"

or, even just "qemu with some asserts" but looking *exactly* like how
it's done in the simulator, right now.

and that ultimately it should be possible to have a runtime switch
(or a suite of tests) that allow us to verify *aaalll* the simulator
test_pipe_caller.py tests, in the following way:

* simulator vs qemu
* qemu vs hardware
* hardware vs simulator

later i would very much like to be able to add microwatt to that list.

-- 
You are receiving this mail because:
You are on the CC list for the bug.


More information about the libre-riscv-dev mailing list