[libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=376

--- Comment #9 from Jacob Lifshay <programmerjake at gmail.com> ---
Additional note: Gigabit ethernet requires 4 tx and 4 rx serdes assuming we
have the PHY integrated on-chip. All 4 twisted pairs are operated in both
directions simultaneously.

See section in https://en.wikipedia.org/wiki/Gigabit_Ethernet#1000BASE-T

If we're integrating our own PHYs, it'd be nice to support 2.5G, 5G, and/or 10G
as well.

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