[libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=376

--- Comment #8 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Jacob Lifshay from comment #7)
> (In reply to Luke Kenneth Casson Leighton from comment #3)
> > i am inclined to seriously recommend at least two separate OMI interfaces
> > (with the option to use them in parallel), one to be connected to a video
> > DRAM chip, the other to be connected to a "OS / GPU" memory DRAM chip,
> > with the option to say "i don't care about that, just use one or both for
> > general shared memory"
> 
> I strongly disagree with the idea of partitioning memory interfaces between
> GPU and CPU tasks, since the processors are designed to do both kinds of
> tasks well and splitting the memory interfaces up is basically saying: "all
> the CPU tasks can't use as much memory bandwidth as GPU tasks just because
> we say so". Also, I envision people building new varieties of tasks that are
> a hybrid between CPU and GPU tasks, so it will be harder to differentiate
> them because of things that fall in the grey areas.

I hadn't considered this. I think that this should be carefully discussed and
considered with someone who is an expert on data and on hardware
interconnects/buses. Rudy is one such person right?

I think the idea of new varieties of hybrid cpu-gpu algorithms is a very
interesting and compelling one. I'd be very interested in what ideas other
experts like those on comp.arch would have.

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