[libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=376

--- Comment #10 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Jacob Lifshay from comment #9)
> Additional note: Gigabit ethernet requires 4 tx and 4 rx serdes assuming we
> have the PHY integrated on-chip. All 4 twisted pairs are operated in both
> directions simultaneously.
> 
> See section in https://en.wikipedia.org/wiki/Gigabit_Ethernet#1000BASE-T
> 
> If we're integrating our own PHYs, it'd be nice to support 2.5G, 5G, and/or
> 10G as well.

Our own PHYs as in have Rudy and SymbyoticEDA design them, or actually doing
them ourselves? ... because from discussion of this from a few months ago it
seems like designing our own PHYs would be a 5+ year undertaking.

The higher speed ethernet interfaces will be very important for the higher
power consumption higher-end market segments. Good idea.

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