[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #39 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #38)
> i'm looking at the 3.0B pseudocode for OP_SC and going "hmmm".
> 
> SC-Form
> 
> * sc LEV
> 
>     SRR0 <-iea CIA + 4

looking at what OP_TRAP does i think we need these 2 extra lines in OP_ SC:

      comb += srr0_o.data.eq(cia_i+4)   # old PC
      comb += srr0_o.ok.eq(1)

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