[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #40 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
OP_RFID POWER9 3.0B pseudocode also has this:

    NIA <-iea SRR0[0:61] || 0b00

oooooo ngggh ok.  so in microwatt they are inputting SRR0 from a_in, and SRR1
from b_in.

we are not going to do that.

so in these lines 193 to 197:

 193                 comb += nia_o.data.eq(br_ext(a_i[2:]))
 194                 comb += nia_o.ok.eq(1)
 195                 for stt, end in [(0,16), (22, 27), (31, 64)]:
 196                     comb += msr_o.data[stt:end].eq(b_i[stt:end])
 197                 with m.If(a[MSR_PR]):

substitute srr0_i for a_i (and a at line 197) and srr1_i for b_i

-- 
You are receiving this mail because:
You are on the CC list for the bug.