[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #41 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;hb=HEAD

for OP_SC, OP_RFID and OP_TRAP we need to set the fast spr fields in DecodeA,
DecodeB and so on, so that the fields are correctly set.

this may involve the CSV files, putting the information there.

example: OP_TRAP needs to output SRR0, therefore DecodeOut needs to set
fast_out to SRR0 when the opcode is OP_TRAP.

-- 
You are receiving this mail because:
You are on the CC list for the bug.