[libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=376

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #15)

> > so 8 pairs at 3.2Gbps is about a watt
> > Can't imagine for 25Gbps

if we assume it's linear: 8x.  8 watts.

that's if it's linear.  (if it's a square law, it's 64 watts.
i don't believe that to be the case).

chances are that it's linear, because the power consumption is
proportional to the amount of change that the signal has to be
dragged up and down.

consequently, we multiply the current draw by 8.

if however the speed of pullup/pulldown has to be *faster* than
it is carried out at 3.2ghz, then we're in trouble.  it might
not be a square-law exactly but it would be close.


> > they might be targeting a different subprocess
> > than us though. I think most fabs offer the
> > options of like "low power", "high performance”,
> >  or "high density"

this will be a dedicated analog block, extremely specialist,
with a full custom layout.

only when you have a digital layout do you have the option
of telling the yosys "synth" command:

* "please can you optimise for lower latency" (i don't care about power)

or

* "please can you optimise for gate reduction" (i don't care about latency)

these give you big and LITTLE respectively... but it's *only* something
you can do for digital layout.

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