[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #55 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #54)
> (In reply to Luke Kenneth Casson Leighton from comment #47)
> > this is going to be a mess.
> > 
> > mtmsr pseudocode:
> > 
> > if L = 0 then
> >     MSR48 <- (RS)48 | (RS)49
> >     MSR58 <- ((RS)58 | (RS)49)
> >         & ¬(MSR41 & MSR3 & (¬(RS)49))
> >     MSR59 <- ((RS)59 | (RS)49)
> >         & ¬(MSR41 & MSR3 & (¬(RS)49))
> >     MSR32:40 42:47 49:50 52:57 60:62
> >        (RS)32:40 42:47 49:50 52:57 60:62
> > else:
> >     MSR48 62 <- (RS)48 62
> > 
> > i forgot to add the pseudocode from mtmsr and mfmsr to the isa markdown
> > files.  the above is note-form from the 3.0B PDF
> > 
> > mfmsr:
> > 
> > RT <- MSR
> 
> Luke, in order to complete task 2 of your last comment, should this be added
> with the note 'Note-Form from the 3.0B PDF' instead of 'X-Form' or
> 'XFX-Form'?

whatever is in the PDF from the spec.  the format however has to be *exactly*
like the others, down to the linebreaks, because it is machine readable.

see pywriter.py,in the top level Makefile.

so you can test it before committing

> 
> Additionally should the pseudo code for OP_SC from comment 38 be added to
> sprset.mdwn as well?

grep sc or scv *.mdwn and you'll find those are in system.mdwn already.

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