[libre-riscv-dev] libresoc memory architecture
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Jun 24 20:42:08 BST 2020
On Wed, Jun 24, 2020 at 7:29 PM Michael Nolan <mtnolan2640 at gmail.com> wrote:
> On 6/24/20 11:50 AM, Luke Kenneth Casson Leighton wrote:
> > i'm transferring the signal comments over to
> > soc.minerva.units.loadstore.LoadStoreUnitInterface.
> Oh thanks. I'm still working on understanding exactly how the
> LoadStoreUnitInterface works exactly, but I'm making some progress I
have a look at core.py in the lambdaconcept minerva repo.
> What really confused me is that the valid and stall signals are
> both inputs indicating whether the pipeline stages are enabled or
yehyeh i know :)
> I'll continue updating the comments in loadstore.py as I figure
> things out.
i can help in a bit
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