[libre-riscv-dev] libresoc memory architecture

[Luke Kenneth Casson Leighton]

On Wed, Jun 24, 2020 at 7:29 PM Michael Nolan <mtnolan2640 at gmail.com> wrote:
>
> On 6/24/20 11:50 AM, Luke Kenneth Casson Leighton wrote:
> > i'm transferring the signal comments over to
> > soc.minerva.units.loadstore.LoadStoreUnitInterface.
> >
> Oh thanks. I'm still working on understanding exactly how the
> LoadStoreUnitInterface works exactly, but I'm making some progress I
> think.

have a look at core.py in the lambdaconcept minerva repo.

> What really confused me is that the valid and stall signals are
> both inputs indicating whether the pipeline stages are enabled or
> stalled.

yehyeh i know :)

> I'll continue updating the comments in loadstore.py as I figure
> things out.

i can help in a bit