[libre-riscv-dev] Successful subscription

[Luke Kenneth Casson Leighton]

On Sun, Jun 7, 2020 at 1:01 AM Sanjay Menon <sanjayamenon.mec at gmail.com> wrote:
>
> Hi,
>
> I did finally manage to get myself subscribed to the mailing list.

hooray! :)  bear in mind that this is considered a high-traffic list.
you may wish to look at setting up filters (gmail can do that) - in
particular i recommend creating a special folder for anything that
comes from the bugzilla libre-soc address.

> Thanks to a little help from Yehowshua.
>
> I would be checking out the nMigen tool.

robert baruch's tutorial is extremely good to get started, yehowshua
sent the link.

the main thing that you need to get your head round for nmigen is that
unlike MyHDL, you *use* python to construct an in-memory Abstract
Syntax Tree.  this AST is then passed to a nmigen function, which
simply walks that AST and outputs yosys ILANG files (or verilog files,
if you ask it to).

MyHDL is a *language translator* (not a compiler) that actually takes
the actual python code and transliterates into VHDL.  thus, in MyHDL,
you absolutely cannot use python exceptions, or many OO techniques,
because those concepts simply do not exist at the Gate Level, in
hardware.

in nmigen we are entirely at liberty to use the *full* capabilities of
python OO programming, and we do so extensively.

the closest that Verilog has to even the most basic capability that we
use all the time in nmigen: parameters in modules.   we also pass
parameters to the class constructor (or a python function) which
changes the size of the array, or the width of the signals, and so on.


> As for my SHA256 IP, I currently have done 2 implementations of the same.
> 1. Using the Vivado HLS environment
> 2. Using Verilog

oh good.  so you're used to working "indirectly", so to speak.  that's
very good.  that experience - writing in C i presume? - then comparing
the same implementation in Verilog - this will stand you in good stead
when working with nmigen.

when you follow robert baruch's tutorial, i recommend you also explore
generating verilog output from the examples, and have a look at what
is produced.  it's... sort-of readable, and you will quickly get used
to seeing how there is a direct equivalence between the nmigen and
verilog.

> Currently working on an implementation of a SHA256 cracker using HLS.

nice :)

l.