[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #36 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
 153                 with m.If(L):
 154                     comb += msr_o[MSR_EE].eq(msr_i[MSR_EE])
 155                     comb += msr_o[MSR_RI].eq(msr_i[MSR_RI])
 156 

look again at the VHDL. it inputs from c_in.  we assigned a_i to that.

here instead the copy is ciming from the incoming msr (msr_i).  clearly thus is
wrong.

line by line.

compare, literally, by putting two fingers pointing one at the VHDL and the
other at the nmigen code, like you are 5 years old learning to read, if you
have to!

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