[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #35 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #34)
> > go MSB -> LSB order, python is LSB->MSB order
> 
> sorry, that should be "python is LSB->MSB+1" order.

I think everything has been brought into line with your suggestions. Please
take a look and let me know if I've made a mistake, I'm specifically not
confident about my putting 'comb += nia_o.data.eq(br_ext(a_i[2:]))' on line
193, in OP_MFMSR.

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