[libre-riscv-dev] Yehowshua Tasks

[Yehowshua]

> 
> what do you think?

> * create a TestMemoryLoadStoreUnit (TMLSU) which is compliant with the
> LSUI interface, but *IGNORES* LSUI's wishbone bus entirely
> * make TMLSU read and write to TestMemory *using* the LSUI x_addr,
> x_mask, etc. etc.

Wait - why not just have TestMemory test 
LSUI connected to memory via wishbone?

That would make sense to me?

I might not be understanding everything here, 
but if we make all memories look like wishbone mems,
whether caches or SRAMS, then the only problem that needs solving
Is ensuring LSUI is wishbone compliant.

However, I remember that we had two caches - that is, the even/odd cache
Thingies connected directly to LDSTunit .

It might make sense to abstract out these with wishbone?
I could be misunderstanding things here.

Yehowshua