[libre-riscv-dev] [Bug 362] New: improvements to nmigen and yosys

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=362

            Bug ID: 362
           Summary: improvements to nmigen and yosys
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

improvements to nmigen and yosys are needed, including CXXSim, a
new backend for yosys that allows a 20 to 100x performance increase
in simulation speed.

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