[libre-riscv-dev] [Bug 369] New: missing XER SO/OV/32 check in test_pipe_caller.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=369

            Bug ID: 369
           Summary: missing XER SO/OV/32 check in test_pipe_caller.py
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/alu/test/test_pipe_caller.py;hb=HEAD

at least ALU and ShiftRot are misding so/ov/32 checking.

test_core.py shows some changes to the XER regfiles that appear not to be
correct, on execution of "adde."

-- 
You are receiving this mail because:
You are on the CC list for the bug.