[libre-riscv-dev] [Bug 369] New: missing XER SO/OV/32 check in test_pipe_caller.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Jun 8 02:09:26 BST 2020


            Bug ID: 369
           Summary: missing XER SO/OV/32 check in test_pipe_caller.py
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---


at least ALU and ShiftRot are misding so/ov/32 checking.

test_core.py shows some changes to the XER regfiles that appear not to be
correct, on execution of "adde."

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