[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #60 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
 161                     with m.If(a_i[MSR_PR]):
 162                         msr_o.data[MSR_EE].eq(1)
 163                         msr_o.data[MSR_IR].eq(1)
 164                         msr_o.data[MSR_DR].eq(1)

and at line 185 comb += is missing

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