[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=353

--- Comment #32 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #30)

> I'm taking a look at regfile.py as well as the proof. Part of the reason you
> see everything failing is that the truth table in the proof isn't right; the
> register file doesn't have a defined output when read enable is low.

the default - because it is combinatorial - will be that the output is
zero when read-enable is low.  we rely on this when it comes to multiple
registers (later) because those zeros are OR-cascaded together (using
ortreereduce) to create the output.

> I have
> an idea as to how to prove that register writes work, would you like me to
> write it?

yes please.  we really need to move on, fast.  RegFileArray *should* be
a lot easier to write (if using the Register as the base)

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