[libre-riscv-dev] IBM releases A2I core VHDL

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Tue, Jun 30, 2020 at 10:06 AM Jacob Lifshay <programmerjake at gmail.com>
wrote:
>
> On Tue, Jun 30, 2020, 01:57 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > On Tue, Jun 30, 2020 at 9:50 AM Luke Kenneth Casson Leighton
> > <lkcl at lkcl.net> wrote:
> > >
> > > On Tue, Jun 30, 2020 at 7:35 AM Lauri Kasanen <cand at gmx.com> wrote:
> > > >
> > > > Hi,
> > > >
> > > > https://github.com/openpower-cores/a2i
> >
> >
> >
https://github.com/openpower-cores/a2i/blob/master/rel/src/vhdl/work/fuq_sto.vhdl
> >
> > holy cow.  they did full gate-level design, effectively.
> >
> > it also looks like the code's been run through a comment-sanitiser,
> > which makes it almost impossible to understand.
> >
>
> Another option is that what they published is the output of a synthesizer.

a synthesiser would not take care in doing this kind of thing:

u_shd04_0: shd04_0_b(0 to 63) <= not( ( lftx04_0_bus(0 to 63) and rolx04_0(0
to 63) ) or ( lftx04_1_bus(0 to 63) and rolx04_1(0 to 63) ) );
( lftx04_1_bus(0 to 63) and rolx04_1(0 to 63) ) );
note the careful use of whitespace - particularly the last "or" lined up
vertically with the right-bracket.  that kind of attention to detail (as
well as some inconsistencies where "rules" like that are not applied) tends
to support the hypothesis that this is genuinely hand-crafted.

> It strikes me as quite odd to include the power lines as inputs and
outputs
> for each logic block, those have always been implicit for languages like
> VHDL or Verilog in my experience.

yehh except they may be doing different voltage domains (core, GPIO) so
consequently they had the team make damn sure they connected up the right
blocks with the right power domains by explicitly naming them.

most "open" code i don't believe has ever involved different voltage
domains for an actual 45nm ASIC.

l.