[libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=376

--- Comment #19 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #17)
> (In reply to Jacob Lifshay from comment #12)
> > Assuming we're building a higher than 2W version, I think we should double
> > the int/fpmul to 8x32-bit per core or maybe even quadruple it to 16x32-bit
> > and add more cores to 8 or 16 or more cores.
> 
> at 2.0 ghz this would start to put out some serious numbers :)

I got 1TFLOP/s for 16 fma/clock/core with 16 cores, that's more than half the
PS4's performance.

> > Also, it might be worthwhile to add one more
> > core and disable one at manufacture time as a way to increase yield.
> 
> that's a good idea.  have to bear in mind that current leakage occurs
> regardless of whether the silicon is in use or not.

If we set up each core as a different power domain (which will also help with
idle power), the disabled core could be powered-down. We would probably want
each core to be it's own clock domain.

We should probably also widen the instruction decoders to decode 3 or 4 32-bit
instructions per cycle.

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